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UJA1079
LIN core system basis chip
Rev. 01 -- 1 December 2009 Product data sheet
1. General description
The UJA1079 core System Basis Chip (SBC) replaces the basic discrete components commonly found in Electronic Control Units (ECU) with a Local Interconnect Network (LIN) interface. The UJA1079 supports the networking applications used to control power and sensor peripherals by using the LIN interface as a local sub-bus. The core SBC contains the following integrated devices:
* LIN transceiver compliant with LIN 2.1, LIN 2.0 and SAE J2602, and compatible with
LIN 1.3
* Advanced independent watchdog (UJA1079/xx/WD versions) * 250 mA voltage regulator for supplying a microcontroller; extendable with external
PNP transistor for increased current capability and dissipation distribution
* Serial peripheral interface (full duplex) * 2 local wake-up input ports * Limp home output port
In addition to the advantages gained from integrating these common ECU functions in a single package, the core SBC offers an intelligent combination of system-specific functions such as:
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* Advanced low-power concept * Safe and controlled system start-up behavior * Detailed status reporting on system and sub-system levels
The UJA1079 is designed to be used in combination with a microcontroller. The SBC ensures that the microcontroller always starts up in a controlled manner.
NXP Semiconductors
UJA1079
LIN core system basis chip
2. Features
2.1 General
Contains LIN ECU functions: LIN transceiver Scalable 3.3 V or 5 V voltage regulator delivering up to 250 mA for a microcontroller and peripheral circuitry; an external PNP transistor can be connected for better heat distribution over the PCB Watchdog with Window and Timeout modes and on-chip oscillator Serial Peripheral Interface (SPI) for communicating with the microcontroller ECU power management system Designed for automotive applications: Excellent ElectroMagnetic Compatibility (EMC) performance 8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) on the LIN bus pin and the WAKE pins 6 kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 on the LIN bus pin and the WAKE pins 58 V short-circuit proof LIN bus pin Battery and LIN bus pins are protected against transients in accordance with ISO 7637-3 Small 6.1 mm x 11 mm HTSSOP32 package with low thermal resistance Pb-free; RoHS and dark green compliant
2.2 LIN transceiver
LIN 2.1 compliant LIN transceiver Compliant with SAE J2602 Downward compatible with LIN 2.0 and LIN 1.3 Low slope mode for optimized EMC performance Integrated LIN termination diode at pin DLIN
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2.3 Power management
Wake-up via LIN or local WAKE pins with wake-up source detection 2 WAKE pins: WAKE1 and WAKE2 inputs can be switched off to reduce current flow Output signal (WBIAS) to bias the WAKE pins, selectable sampling time of 16 ms or 64 ms Standby mode with very low standby current and full wake-up capability; V1 active to maintain supply to the microcontroller Sleep mode with very low sleep current and full wake-up capability
2.4 Control and Diagnostic features
Safe and predictable behavior under all conditions Programmable watchdog with independent clock source
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UJA1079
LIN core system basis chip
Window, Timeout (with optional cyclic wake-up) and Off modes supported (with automatic re-enable in the event of an interrupt) 16-bit Serial Peripheral Interface (SPI) for configuration, control and diagnosis Global enable output for controlling safety-critical hardware Limp home output (LIMP) for activating application-specific `limp home' hardware in the event of a serious system malfunction Overtemperature shutdown Interrupt output pin; interrupts can be individually configured to signal V1 undervoltage, LIN/local wake-up and cyclic and power-on interrupt events Bidirectional reset pin with variable power-on reset length to support a variety of microcontrollers Software-initiated system reset
2.5 Voltage regulator V1
Scalable voltage regulator for the microcontroller, its peripherals and additional external transceivers 2 % accuracy for LIN master application 3 % accuracy for LIN slave application 3.3 V and 5 V versions available Delivers up to 250 mA and can be combined with an external PNP transistor for better heat distribution over the PCB Selectable current threshold at which the external PNP transistor starts to deliver current Undervoltage warning at 90 % of nominal output voltage and undervoltage reset at 90 % or 70 % of nominal output voltage Can operate at VBAT voltages down to 4.5 V (e.g. during cranking), in accordance with ISO7637 pulse 4/4b and ISO16750-2 Stable output under all conditions
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3. Ordering information
Table 1. Ordering information Package Name UJA1079TW/5V0/WD UJA1079TW/3V3/WD UJA1079TW/5V0 UJA1079TW/3V3
[1] UJA1079TW/5V0xx versions contain a 5 V regulator (V1); UJA1079TW/3V3xx versions contain a 3.3 V regulator (V1); WD versions contain a watchdog.
Type number
Description plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
Version SOT549-1
HTSSOP32
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UJA1079
LIN core system basis chip
4. Block diagram
UJA1079
BAT V1 V1
GND V1 UV EXT. PNP CTRL VEXCTRL VEXCC WBIAS
SCK SDI SDO SCSN WAKE1 WAKE2 WDOFF EN DLIN LIN TXDL RXDL LIN BAT BAT WAKE SYSTEM CONTROLLER
INTN RSTN OSC TEMP LIMP
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Fig 1.
Block diagram
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5. Pinning information
5.1 Pinning
i.c. i.c. TXDL V1 RXDL RSTN INTN EN SDI
1 2 3 4 5 6 7 8 9
32 BAT 31 VEXCTRL 30 TEST2 29 VEXCC 28 WBIAS 27 i.c. 26 DLIN 25 LIN 24 i.c. 23 GND 22 i.c. 21 i.c. 20 i.c. 19 WAKE2 18 WAKE1 17 LIMP
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UJA1079
SDO 10 SCK 11 SCSN 12 i.c. 13 i.c. 14 TEST1 15 WDOFF 16
Fig 2.
Pin configuration
5.2 Pin description
Table 2. Symbol i.c.
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Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Description internally connected; should be left floating internally connected; should be left floating LIN transmit data input voltage regulator output for the microcontroller (5 V or 3.3 V depending on SBC version) LIN receive data output reset input/output to and from the microcontroller interrupt output to the microcontroller enable output SPI data input SPI data output SPI clock input SPI chip select input internally connected; should be left floating internally connected; should be left floating test pin; pin should be connected to ground WDOFF pin for deactivating the watchdog limp home output
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i.c. TXDL V1 RXDL RSTN INTN EN SDI SDO SCK SCSN i.c. i.c. TEST1 WDOFF LIMP
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LIN core system basis chip
Pin description ...continued Pin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Description local wake-up input 1 local wake-up input 2 internally connected; should be left floating internally connected; should be left floating internally connected; should be left floating ground internally connected; should be left floating LIN bus line LIN termination resistor connection internally connected; should be left floating control pin for external wake biasing transistor current measurement for external PNP transistor; this pin is connected to the collector of the external PNP transistor test pin; pin should be connected to ground control pin of the external PNP transistor; this pin is connected to the base of the external PNP transistor battery supply for the SBC
Table 2. Symbol WAKE1 WAKE2 i.c. i.c. i.c. GND i.c. LIN DLIN i.c. WBIAS VEXCC TEST2 VEXCTRL BAT
The exposed die pad at the bottom of the package allows for better heat dissipation from the SBC via the printed circuit board. The exposed die pad is not connected to any active part of the IC and can be left floating, or can be connected to GND.
6. Functional description
The UJA1079 combines the functionality of a LIN transceiver, a voltage regulator and a watchdog (UJA1079/xx/WD versions) in a single, dedicated chip. It handles the power-up and power-down functionality of the ECU and ensures advanced system reliability. The SBC offers wake-up by bus activity, by cyclic wake-up and by the activation of external switches. Additionally, it provides a periodic control signal for pulsed testing of wake-up switches, allowing low-current operation even when the wake-up switches are closed in Standby mode. The LIN transceiver is optimized to be highly flexible with regard to bus topologies. V1, the voltage regulator, is designed to power the ECU's microcontroller, its peripherals and additional external transceivers. An external PNP transistor can be added to improve heat distribution. The watchdog is clocked directly by the on-chip oscillator and can be operated in Window, Timeout and Off modes.
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6.1 System Controller
6.1.1 Introduction
The system controller manages register configuration and controls the internal functions of the SBC. Detailed device status information is collected and presented to the microcontroller. The system controller also provides the reset and interrupt signals.
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UJA1079
LIN core system basis chip
The system controller is a state machine. The SBC operating modes, and how transitions between modes are triggered, are illustrated in Figure 3. These modes are discussed in more detail in the following sections.
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LIN core system basis chip
from Standby or Normal
VBAT below power-off threshold Vth(det)poff (from all modes)
Overtemp
V1: OFF limp home = LOW (active) LIN: Off and high resistance watchdog: OFF
chip temperature above OTP activatrion threshold Tth(act)otp
Off
V1: OFF LIN: Off and high resistance watchdog: OFF INTN: HIGH
chip temperature below OTP release threshold Tth(rel)otp
VBAT below power-on threshold Vth(det)pon
VBAT above power-on threshold Vth(det)pon
watchdog overflow or V1 undervoltage
watchdog trigger
Standby
V1: ON LIN: Lowpower/Off watchdog: Timeout/Off MC = 00
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MC = 01 and INTN = HIGH and one wake-up enabled and no wake-up pending
reset event or MC = 00
MC = 10 or MC = 11
wake-up event if enabled
Normal
successful watchdog trigger V1: ON LIN: Active/Lowpower watchdog: Window/ Timeout/Off MC = 1x
Sleep
V1: OFF LIN: Lowpower/Off watchdog: OFF RSTN: LOW MC = 01
MC = 01 and INTN = HIGH and one wake-up enabled and no wake-up pending
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Fig 3.
UJA1079 system controller
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6.1.2 Off mode
The SBC switches to Off mode from all other modes if the battery supply drops below the power-off detection threshold (Vth(det)poff). In Off mode, the voltage regulator is disabled and the bus system is in a high-resistive state. As soon as the battery supply rises above the power-on detection threshold (Vth(det)pon), the SBC goes to Standby mode, and a system reset is executed (reset pulse width of tw(rst), long or short; see Section 6.5.1 and Table 10).
6.1.3 Standby mode
The SBC will enter Standby mode:
* From Off mode if VBAT rises above the power-on detection threshold (Vth(det)pon) * From Sleep mode on the occurrence of a LIN or local wake-up event * From Overtemp mode if the chip temperature drops below the overtemperature
protection release threshold, Tth(rel)otp
* From Normal mode if bit MC is set to 00 or a system reset is performed (see
Section 6.5) In Standby mode, V1 is switched on. The LIN transceiver will either be in a low-power state (Lowpower mode; STBCL = 1; see Table 6) with bus wake-up detection enabled or completely switched off (Off mode; STBCL = 0) - see Section 6.7.1. The watchdog can be running in Timeout mode or Off mode, depending on the state of the WDOFF pin and the setting of the watchdog mode control bit (WMC) in the WD_and_Status register (Table 4). The SBC will exit Standby mode if:
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* Normal mode is selected by setting bits MC to 10 or 11 * Sleep mode is selected by setting bits MC to 01 * The chip temperature rises above the OTP activation threshold, Tth(act)otp, causing the
SBC to enter Overtemp mode
6.1.4 Normal mode
Normal mode is selected from Standby mode by setting bits MC in the Mode_Control register (Table 5) to 10 or 11. In Normal mode, the LIN physical layer (LIN) will be enabled (Active mode; STBCL = 0; see Table 6) or in a low-power state (Lowpower mode; STBCL = 1) with bus wake-up detection active. The SBC will exit Normal mode if:
* * * *
Standby mode is selected by setting bits MC to 00 Sleep mode is selected by setting bits MC to 01 A system reset is generated (see Section 6.1.3; the SBC will enter Standby mode) The chip temperature rises above the OTP activation threshold, Tth(act)otp, causing the SBC to switch to Overtemp mode
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6.1.5 Sleep mode
Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the Mode_Control register (Table 5) to 01. The SBC will enter Sleep mode providing there are no pending interrupts (INTN = HIGH) or wake-up events and at least one wake-up source is enabled (LIN or WAKE). Any attempt to enter Sleep mode while one of these conditions has not been satisfied will result in a short reset (3.6 ms min. pulse width; see Section 6.5.1 and Table 10). In Sleep mode, V1 is off and the LIN transceiver will be switched off (Off mode; STBCL = 0; see Table 6) or in a low-power state (Lowpower mode; STBCL = 1) with bus wake-up detection active - see Section 6.7.1). The watchdog is off and the reset pin is LOW. A LIN or local wake-up event will cause the SBC to switch from Sleep mode to Standby mode, generating a (short or long; see Section 6.5.1) system reset. The value of the mode control bits (MC) will be changed to 00 and V1 will be enabled.
6.1.6 Overtemp mode
The SBC will enter Overtemp mode from Normal mode or Standby mode when the chip temperature exceeds the overtemperature protection activation threshold, Tth(act)otp, In Overtemp mode, the voltage regulator is switched off and the bus system is in a high-resistive state. When the SBC enters Overtemp mode, the RSTN pin is driven LOW and the limp home control bit, LHC, is set so that the LIMP pin is driven LOW. The chip temperature must drop a hysteresis level below the overtemperature shutdown threshold before the SBC can exit Overtemp mode. After leaving Overtemp mode the SBC enters Standby mode and a system reset is generated (reset pulse width of tw(rst), long or short; see Section 6.5.1 and Table 10).
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6.2 SPI
6.2.1 Introduction
The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave operations. The SPI is configured for full duplex data transfer, so status information is returned when new control data is shifted in. The interface also offers a read-only access option, allowing registers to be read back by the application without changing the register content. The SPI uses four interface signals for synchronization and data transfer:
* * * *
SCSN - SPI chip select; active LOW SCK - SPI clock; default level is LOW due to low-power concept SDI - SPI data input SDO - SPI data output; floating when pin SCSN is HIGH
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock edge (see Figure 4).
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LIN core system basis chip
SCS
SCK
01 sampled
02
03
04
15
16
SDI
X
MSB
14
13
12
01
LSB
X
SDO
floating
X
MSB
14
13
12
01
LSB
floating
mce634
Fig 4.
SPI timing protocol
6.2.2 Register map
The first three bits (A2, A1 and A0) of the message header define the register address. The fourth bit (RO) defines the selected register as read/write or read only.
Table 3. 000 001 010 011 Register map Write access bit 12 = 0 0 = read/write, 1 = read only 0 = read/write, 1 = read only 0 = read/write, 1 = read only 0 = read/write, 1 = read only Read/Write access bits 11... 0 WD_and_Status register Mode_Control register Int_Control register Int_Status register
Address bits 15, 14 and 13
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6.2.3 WD_and_Status register
Table 4. Bit WD_and_Status register Access Power-on Description default R R/W 000 0 register address access status 0: register set to read/write 1: register set to read only 11 WMC R/W 0 watchdog mode control 0: Normal mode: watchdog in Window mode; Standby mode: watchdog in Timeout mode 1: Normal mode: watchdog in Timeout mode; Standby mode: watchdog in Off mode 10:8 NWP[1] R/W 100 nominal watchdog period 000: 8 ms 001: 16 ms 010: 32 ms 011: 64 ms 100: 128 ms 101: 256 ms 110: 1024 ms 111: 4096 ms 7 SWR/WOS R/W software reset/watchdog off status 0: WDOFF pin LOW; watchdog mode determined by bit WMC 1: watchdog disabled due to HIGH level on pin WDOFF; results in software reset 6 V1S www..com R V1 status 0: V1 output voltage above 90 % undervoltage recovery threshold (Vuvr; see Table 9) 1: V1 output voltage below 90 % undervoltage detection threshold (Vuvd; see Table 9) 5 4 reserved WLS1 R R 1 wake-up1 status 0: WAKE1 input voltage below switching threshold (Vth(sw)) 1: WAKE1 input voltage above switching threshold (Vth(sw)) 3 WLS2 R wake-up 2 status 0: WAKE2 input voltage below switching threshold (Vth(sw)) 1: WAKE2 input voltage above switching threshold (Vth(sw)) 2:0
[1]
Symbol
15:13 A2, A1, A0 12 RO
reserved
R
000
Bit NWP is set to it's default value (100) after a reset.
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6.2.4 Mode_Control register
Table 5. Bit 15:13 12 Mode_Control register Symbol Access Power-on default 001 0 R/W Description register address access status 0: register set to read/write 1: register set to read only 11:10 MC R/W 00 mode control 00: Standby mode 01: Sleep mode 10: Normal mode 11: Normal mode 9 LHWC[1] R/W 1 limp home warning control 0: no limp home warning 1: limp home warning is set; next reset will activate LIMP output 8 LHC[2] R/W 0 limp home control 0: LIMP pin set floating 1: LIMP pin driven LOW 7 ENC R/W 0 enable control 0: EN pin driven LOW 1: EN pin driven HIGH in Normal mode 6 LSC R/W 0 LIN slope control 0: normal slope, 20 kbit/s 1: low slope, 10.4 kbit/s
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A2, A1, A0 R RO
5
WBC
R/W
0
wake bias control 0: WBIAS floating if WSEn = 0; 16 ms sampling if WSEn = 1 1: WBIAS on if WSEn = 0; 64 ms sampling if WSEn = 1
4
PDC
R/W
0
power distribution control 0: V1 threshold current for activating the external PNP transistor; load current rising; Ith(act)PNP = 85 mA; V1 threshold current for deactivating the external PNP transistor; load current falling; Ith(deact)PNP = 50 mA; see Figure 7 1: V1 threshold current for activating the external PNP transistor; load current rising; Ith(act)PNP = 50 mA; V1 threshold current for deactivating the external PNP transistor; load current falling; Ith(deact)PNP = 15 mA; see Figure 7
3:0
[1] [2]
reserved
R
0000
Bit LHWC is set to 1 after a reset. Bit LHC is set to 1 after a reset, if LHWC was set to 1 prior to the reset.
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6.2.5 Int_Control register
Table 6. Bit 15:13 12 Int_Control register Symbol Access Power-on default 010 0 R/W Description register address access status 0: register set to read/write 1: register set to read only 11 V1UIE R/W 0 V1 undervoltage interrupt enable 0: V1 undervoltage warning interrupts cannot be requested 1: V1 undervoltage warning interrupts can be requested 10 9 reserved STBCL R R/W 0 0 LIN standby control 0: When the SBC is in Normal mode (MC = 1x): LIN is in Active mode. The wake-up flag (visible on RXDL) is cleared regardless of the value of VBAT. When the SBC is in Standby/Sleep mode (MC = 0x): LIN is in Off mode. Bus wake-up detection is disabled. LIN wake-up interrupts cannot be requested. 1: LIN is in Lowpower mode with bus wake-up detection enabled, regardless of the SBC mode (MC = xx). LIN wake-up interrupts can be requested. 8 7:6 reserved WIC1 R R/W 0 00 wake-up interrupt 1 control 00: wake-up interrupt 1 disabled 01: wake-up interrupt 1 on rising edge 10: wake-up interrupt 1 on falling edge
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A2, A1, A0 R RO
11: wake-up interrupt 1 on both edges R/W 00 wake-up interrupt 2 control 00: wake-up interrupt 2 disabled 01: wake-up interrupt 2 on rising edge 10: wake-up interrupt 2 on falling edge 11: wake-up interrupt 2 on both edges
5:4
WIC2
3 2
reserved RTHC
R R/W
0 0 reset threshold control 0: The reset threshold is set to the 90 % V1 undervoltage detection voltage (Vuvd; see Table 9) 1: The reset threshold is set to the 70 % V1 undervoltage detection voltage (Vuvd; see Table 9)
1
WSE1
R/W
0
WAKE1 sample enable 0: sampling continuously 1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled by WBC)
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Table 6. Bit 0
Int_Control register Symbol WSE2 Access Power-on default R/W 0 Description WAKE2 sample enable 0: sampling continuously 1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled by WBC)
6.2.6 Int_Status register
Table 7. Bit 15:13 12 Int_Status register[1] Symbol Access Power-on default 011 0 R/W Description register address access status 0: register set to read/write 1: register set to read only 11 V1UI R/W 0 V1 undervoltage interrupts 0: no V1 undervoltage warning interrupt pending 1: V1 undervoltage warning interrupt pending 10 9 reserved LWI R R/W 0 0 LIN wake-up interrupt 0: no LIN wake-up interrupt pending 1: LIN wake-up interrupt pending 8 7 reserved CI R R/W 0 0 cyclic interrupt 0: no cyclic interrupt pending
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A2, A1, A0 R RO
1: cyclic interrupt pending R/W 0 wake-up interrupt 1 0: no wake-up interrupt 1 pending 1: wake-up interrupt 1 pending
6
WI1
5
POSI
R/W
1
power-on status interrupt 0: no power-on interrupt pending 1: power-on interrupt pending
4
WI2
R/W
0
wake-up interrupt 2 0: no wake-up interrupt 2 pending 1: wake-up interrupt 2 pending
3:0
[1]
reserved
R
0000
An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register.
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6.3 On-chip oscillator
The on-chip oscillator provides the timing reference for the on-chip watchdog and the internal timers. The on-chip oscillator is supplied by an internal supply that is connected to VBAT and is independent of V1.
6.4 Watchdog (UJA1079/xx/WD versions)
Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Table 4). The default watchdog period is 128 ms. A watchdog trigger event is any write access to the WD_and_Status register. When the watchdog is triggered, the watchdog timer is reset. In watchdog Window mode, a watchdog trigger event within a closed watchdog window (i.e. the first half of the window before ttrig(wd)1) will generate an SBC reset. If the watchdog is triggered before the watchdog timer overflows in Timeout or Window mode, or within the open watchdog window (after ttrig(wd)1 but before ttrig(wd)2), the timer restarts immediately. The following watchdog events result in an immediate system reset:
* * * * *
the watchdog overflows in Window mode the watchdog is triggered in the first half of the watchdog period in Window mode the watchdog overflows in Timeout mode while a cyclic interrupt (CI) is pending the state of the WDOFF pin changes in Normal mode or Standby mode the watchdog mode control bit (WMC) changes state in Normal mode
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After a watchdog reset (short reset; see Section 6.5.1 and Table 10), the default watchdog period is selected (NWP = 100). The watchdog can be switched off completely by forcing pin WDOFF HIGH. The watchdog can also be switched off by setting bit WMC to 1 in Standby mode. If the watchdog was turned off by setting WMC, any pending interrupt will re-enable it. Note that the state of bit WMC cannot be changed in Standby mode if an interrupt is pending. Any attempt to change WMC when an interrupt is pending will be ignored.
6.4.1 Watchdog Window behavior
The watchdog runs continuously in Window mode. If the watchdog overflows, or is triggered in the first half of the watchdog period (less than ttrig(wd)1 after the start of the watchdog period), a system reset will be performed. Watchdog overflow occurs if the watchdog is not triggered within ttrig(wd)2 after the start of watchdog period. If the watchdog is triggered in the second half of the watchdog period (at least ttrig(wd)1, but not more than ttrig(wd)2, after the start of the watchdog period), the watchdog will be reset. The watchdog is in Window mode when pin WDOFF is LOW, the SBC is in Normal mode and the watchdog mode control bit (WMC) is set to 0.
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6.4.2 Watchdog Timeout behavior
The watchdog runs continuously in Timeout mode. It can be reset at any time by a watchdog trigger. If the watchdog overflows, the cyclic interrupt (CI) bit is set. If a CI is already pending, a system reset is performed. The watchdog is in Timeout mode when pin WDOFF is LOW and:
* the SBC is in Standby mode and bit WMC = 0 or * the SBC is in Normal mode and bit WMC = 1
6.4.3 Watchdog Off behavior
The watchdog is disabled in this state. The watchdog is in Off mode when:
* the SBC is in Off, Overtemp or Sleep modes * the SBC is in Standby mode and bit WMC = 1 * the SBC is in any mode and the WDOFF pin is HIGH 6.5 System reset
The following events will cause the SBC to perform a system reset:
* V1 undervoltage (reset pulse length selected via external pull-up resistor on RSTN
pin)
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* * * * * * * *
An external reset (RSTN forced LOW) Watchdog overflow (Window mode) Watchdog overflow in Timeout mode with cyclic interrupt (CI) pending Watchdog triggered too early in Window mode WMC value changed in Normal mode WDOFF pin state changed SBC goes to Sleep mode (MC set to 01; see Table 5) while INTN is driven LOW SBC goes to Sleep mode (MC set to 01; see Table 5) while STBCL = WIC1 = WIC2 = 0
* SBC goes to Sleep mode (MC set to 01; see Table 5) while wake-up pending * Software reset (SWR = 1) * SBC leaves Overtemp mode (reset pulse length selected via external pull-up resistor
on RSTN pin) A watchdog overflow in Timeout mode requests a cyclic interrupt (CI), if a CI is not already pending. The UJA1079 provides three signals for dealing with reset events:
* RSTN input/output for performing a global ECU system reset or forcing an external
reset
* EN pin, a fail-safe global enable output * LIMP pin, a fail-safe limp home output
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LIN core system basis chip
6.5.1 RSTN pin
A system reset is triggered if the bidirectional RSTN pin is forced LOW for at least tfltr by the microcontroller (external reset). A reset pulse is output on RSTN by the SBC when a system reset is triggered internally. The reset pulse width (tw(rst)) is selectable (short or long) if the system reset was generated by a V1 undervoltage event (see Section 6.6.2) or by the SBC leaving Off (VBAT > Vth(det)pon) or Overtemp (temperature < Tth(rel)otp) modes. A short reset pulse is selected by connecting a 900 10 % resistor between pins RSTN and V1. If a resistor is not connected, the reset pulse will be long (see Table 10). In all other cases (e.g. watchdog-related reset events) the reset pulse length will be short.
6.5.2 EN output
The EN pin can be used to control external hardware, such as power components, or as a general-purpose output when the system is running properly. In Normal and Standby modes, the microcontroller can set the EN control bit (bit ENC in the Mode_Control register; see Table 5) via the SPI interface. Pin EN will be HIGH when ENC = 1 and MC = 10 or 11. A reset event will cause pin EN to go LOW. EN pin behavior is illustrated in Figure 5.
mode
STANDBY
NORMAL
STANDBY
ENC
EN RSTN
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015aaa074
Fig 5.
Behavior of EN pin
6.5.3 LIMP output
The LIMP pin can be used to enable the so called `limp home' hardware in the event of an ECU failure. Detectable failure conditions include SBC overtemperature events, loss of watchdog service, RSTN or V1 clamped LOW and user-initiated or external reset events. The LIMP pin is a battery-related, active-LOW, open-drain output. A system reset will cause the limp home warning control bit (bit LHWC in the Mode_Control register; see Table 5) to be set. If LHWC is already set when the system reset is generated, bit LHC will be set which will force the LIMP pin LOW. The application should clear LHWC after each reset event to ensure the LIMP output is not activated during normal operation. In Overtemp mode, bit LHC is always set and, consequently, the LIMP output is always active. If the application manages to recover from the event that activated the LIMP output, LHC can be cleared to deactivate the LIMP output.
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6.6 Power supplies
6.6.1 Battery pin (BAT)
The SBC contains a single supply pin, BAT. An external diode is needed in series to protect the device against negative voltages. The operating range is from 4.5 V to 28 V. The SBC can handle maximum voltages up to 40 V. If the voltage on pin BAT falls below the power-off detection threshold, Vth(det)poff, the SBC immediately enters Off mode, which means that the voltage regulator and the internal logic are shut down. The SBC leaves Off mode for Standby mode as soon as the voltage rises above the power-on detection threshold, Vth(det)pon. The POSI bit in the Int_Status register is set to 1 when the SBC leaves Off mode.
6.6.2 Voltage regulator V1
Voltage regulator V1 is intended to supply the microcontroller, its periphery and additional transceivers. V1 is supplied by pin BAT and delivers up to 250 mA at 3.3 V or 5 V (depending on the UJA1079 version). To prevent the device overheating at high ambient temperatures or high average currents, an external PNP transistor can be connected as illustrated in Figure 6. In this configuration, the power dissipation is distributed between the SBC and the PNP transistor. Bit PDC in the Mode_Control register (Table 5) is used to regulate how the power dissipation is distributed - if PDC = 0, the PNP transistor will be activated when the load current reaches 85 mA (50 mA if PDC = 1) at Tvj = 150 C. V1 will continue to deliver 85 mA while the transistor delivers the additional load current (see Figure 7 and Figure 8).
battery
VEXCTRL VEXCC
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BAT
UJA107x
V1
015aaa098
Fig 6.
External PNP transistor control circuit
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LIN core system basis chip
250 mA 215 mA
85 mA load current
50 mA
Ith(act)PNP = 85 mA (PDC = 0) IV1 165 mA
Ith(deact)PNP = 50 mA (PDC = 0)
PNP current
015aaa111
Fig 7.
V1 and PNP currents at a slow ramping load current of 250 mA (PDC = 0)
Figure 7 illustrates how V1 and the PNP transistor combine to supply a slow ramping load current of 250 mA with PDC = 0. Any additional load current requirement will be supplied by the PNP transistor, up to its current limit. If the load current continues to rise, IV1 will increase above the selected PDC threshold (to a maximum of 250 mA). For a fast ramping load current, V1 will deliver the required load current (to a maximum of 250 mA) until the PNP transistor has switched on. Once the transistor has been activated, V1 will deliver 85 mA (PDC = 0) with the transistor contributing the balance of the load current (see Figure 8).
250 mA
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load current
250 mA Ith(act)PNP = 85 mA (PDC = 0) IV1 0 mA
-165 mA
165 mA PNP current
015aaa075
Fig 8.
V1 and PNP currents at a fast ramping load current of 250 mA (PDC = 0)
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For short-circuit protection, a resistor needs to be connected between pins V1 and VEXCC to allow the current to be monitored. This resistor limits the current delivered by the external transistor. If the voltage difference between pins VEXCC and V1 reaches Vth(act)Ilim, the PNP current limiting activation threshold voltage, the transistor current will not increase further. The thermal performance of the transistor needs to be considered when calculating the value of this resistor. A 3.3 resistor was used with the BCP52-16 (NXP Semiconductors) employed during testing. Note that the selection of the transistor is not critical. In general, any PNP transistor with a current amplification factor () of between 60 and 500 can be used. If an external PNP transistor is not used, pin VEXCC must be connected to V1 while pin VEXCTRL can be left open. One advantage of this scalable voltage regulator concept is that there are no PCB layout restrictions when using the external PNP. The distance between the UJA1079 and the external PNP doesn't affect the stability of the regulator loop because the loop is realized within the UJA1079. Therefore, it is recommended that the distance between the UJA1079 and PNP transistor be maximized for optimal thermal distribution. The output voltage on V1 is monitored continuously and a system reset signal is generated if an undervoltage event occurs. A system reset is generated if the voltage on V1 falls below the undervoltage detection voltage (Vuvd; see Table 9). The reset threshold (90 % or 70 % of the nominal value) is set via the Reset Threshold Control bit (RTHC) in the Int_Control register (Table 6). In addition, an undervoltage warning (a V1UI interrupt) will be generated at 90 % of the nominal output voltage. The status of V1 can be read via bit V1S in the WD_and_Status register (Table 4).
6.7 LIN transceiver
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The analog section of the UJA1079 LIN transceiver is identical to that integrated into the TJA1021. The transceiver is the interface between the LIN master/slave protocol controller and the physical bus in a LIN. It is primarily intended for in-vehicle sub-networks using baud rates from 1 kBd up to 20 kBd and is LIN 2.0/LIN 2.1/SAE J2602 compliant.
6.7.1 LIN operating modes
6.7.1.1 Active mode The LIN transceiver will be in Active mode when:
* the SBC is in Normal mode (MC = 10 or 11) and * the transceiver is enabled (STBCL = 0; see Table 6) and * the battery voltage (VBAT) is above the LIN undervoltage recovery threshold, Vuvr(LIN).
In LIN Active mode, the transceiver can transmit and receive data via the LIN bus pin. The receiver detects data streams on the LIN bus pin (LIN) and transfers them to the microcontroller via pins RXDL (see Figure 1) - LIN recessive is represented by a HIGH level on RXDL, LIN dominant by a LOW level.
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The transmit data streams of the protocol controller at the TXDL input are converted by the transmitter into bus signals with optimized slew rate and wave shaping to minimize EME. 6.7.1.2 Lowpower/Off modes The LIN transceiver will be in Lowpower mode with bus wake-up detection enabled if bit STBCL = 1 (see Table 6). The LIN transceiver can be woken up remotely via pin LIN in Lowpower mode. When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the LIN transceiver will be in Off mode if bit STBCL = 0. The LIN transceiver is powered down completely in Off mode to minimize quiescent current consumption. Filters at the receiver inputs prevent unwanted wake-up events due to automotive transients or EMI. The wake-up event must remain valid for at least the minimum dominant bus time, tbus(dom)(min), for wake-up of the LIN transceiver (see Table 10).
6.7.2 Fail-safe features
6.7.2.1 General fail-safe features The following fail-safe features have been implemented:
* Pin TXDL has an internal pull-up towards VV1 to guarantee safe, defined states if
these pins are left floating
* The current of the transmitter output stage is limited in order to protect the transmitter
against short circuits to pin BAT
* A loss of power (pins BAT and GND) has no impact on the bus lines or on the
microcontroller. There will be no reverse currents from the bus. 6.7.2.2 www..com TXDL dominant time-out function A TXDL dominant time-out timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network communications) if TXDL is forced permanently LOW by a hardware and/or software application failure. The timer is triggered by a negative edge on the TXDL pin. If the pin remains LOW for longer than the TXDL dominant time-out time (tto(dom)TXDL), the transmitter is disabled, driving the bus lines to a recessive state. The timer is reset by a positive edge on the TXDL pin.
6.8 Local wake-up input
The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity (falling, rising or both) of the wake-up pins can be configured independently via the WIC1 and WIC2 bits in the Int_Control register Table 6). These bits can also be used to disable wake-up via the wake-up pins. When wake-up is enabled, a valid wake-up event on either of these pins will cause a wake-up interrupt to be generated in Standby mode or Normal mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and enter Standby mode. The status of the wake-up pins can be read via the wake-up level status bits (WLS1 and WLS2) in the WD_and_Status register (Table 4). Note that bits WLS1 and WLS2 are only active when at least one of the wake up interrupts is enabled (WIC1 00 or WIC2 00).
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enable bias WBIASI (internal)
disable bias
WBIAS pin
WAKEx pin
Wake-up int disable bias wake level latched
015aaa078
Fig 9.
Wake-up pin sampling synchronized with WBIAS signal
The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are sampled continuously). The sampling will be performed on the rising edge of WBIAS (see Figure 9). The sampling time, 16 ms or 64 ms, is selected via the Wake Bias Control bit (WBC) in the Mode_Control register. Figure 10 shows typical circuit for implementing cyclic sampling of the wake-up inputs.
UJA1079
BAT
47 k
PDTA144E
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WBIAS
47 k
biasing of switches
WAKE1
t
WAKE2
sample of WAKEx
sample of WAKEx
sample of WAKEx
GND
015aaa126
Fig 10. Typical application for cyclic sampling of wake-up signals
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6.9 Interrupt output
Pin INTN is an active-LOW, open-drain interrupt output. It is driven LOW when at least one interrupt is pending. An interrupt can be cleared by writing 1 to the corresponding bit in the Int_Status register (Table 7). Clearing bit LWI in Standby mode only clears the interrupt status bit and not the pending wake-up. The pending wake-up is cleared on entering Normal mode and when the corresponding standby control bit (STBCL) is 0. On devices that contain a watchdog, the Cyclic Interrupt (CI) is enabled when the watchdog switches to Timeout mode while the SBC is in Standby mode or Normal mode (provided WDOFF = LOW). A CI is generated if the watchdog overflows in Timeout mode. The CI is provided to alert the microcontroller when the watchdog overflows in Timeout mode. The CI will wake up the microcontroller from a C standby mode. After polling the Int_Status register, the microcontroller will be aware that the application is in cyclic wake up mode. It can then perform some checks on LIN before returning to the C standby mode.
6.10 Temperature protection
The temperature of the SBC chip is monitored in Normal and Standby modes. If the temperature is too high, the SBC will go to Overtemp mode, where the RSTN pin is driven LOW and limp home is activated. In addition, the voltage regulator and the LIN transmitter are switched off (see also Section 6.1.6 "Overtemp mode"). When the temperature falls below the temperature shutdown threshold, the SBC will go into the Standby mode. The temperature shutdown threshold is between 165 C and 200 C.
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7. Limiting values
Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Vx Parameter voltage on pin x Conditions DC value pins V1 and INTN pins EN, SDI, SDO, SCK, SCSN, TXDL, RXDL, RSTN and WDOFF pin VEXCC pins WAKE1, WAKE2, WBIAS and LIN; with respect to any other pin pin LIMP and BAT pin VEXCTRL pin DLIN; with respect to any other pin IR(V1-BAT) IDLIN Vtrt reverse current from pin V1 to pin BAT current on pin DLIN transient voltage on pins BAT: via reverse polarity diode/capacitor LIN: coupling via 1 nF capacitor DLIN: via 1 k resistor VESD electrostatic discharge voltage IEC 61000-4-2 pins BAT and LIN; via a series resistor on pins DLIN, WAKE1, WAKE2, LIMP and WBIAS; via transistor on pin VEXCTRL HBM
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[3] [4] [2] [1]
Min -0.3 -0.3 VV1 - 0.3 -58 -0.3 -0.3 -65 -150
Max 7 VV1 + 0.3
Unit V V
VV1 + 0.35 V +58 +40 VBAT + 0.3 25 0 +100 V V V V mA mA V
VBAT - 0.3 +58
-6
+6
kV
[5] [6]
pins LIN, DLIN, WAKE1 and WAKE2 pin TEST2; referenced to pin BAT pin TEST2; referenced to other reference pins any other pin MM any pin CDM corner pins any other pin
-8 -1.25 -2 -2
+8 +2 +2 +2 +300 +750 +500 +150 +150
kV kV kV kV V V V C C
[7]
-300
[8]
-750 -500
[9]
Tvj Tstg
virtual junction temperature storage temperature
-40 -55
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Table 8. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Tamb Parameter ambient temperature Conditions Min -40 Max +125 Unit C
[1] [2] [3] [4] [5] [6] [7] [8] [9]
A reverse diode connected between V1 (anode) and BAT (cathode) limits the voltage drop voltage from V1(+) to BAT (-). Verified by an external test house to ensure pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b. IEC 61000-4-2 (150 pF, 330 ). ESD performance according to IEC 61000-4-2 (150 pF, 330 ) has been verified by an external test house for pins BAT, LIN, WAKE1 and WAKE2. The result is equal to or better than 6 kV. Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k). V1 and BAT connected to GND, emulating application circuit. Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 H, 10 ). Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF). In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P x Rth(vj-a), where Rth(vj-a) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
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8. Thermal characteristics
optional heatsink top layer
PCB copper area: (bottom layer) 2 cm2
optional heatsink top layer
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optional heatsink top layer PCB copper area: (bottom layer) 8 cm2
015aaa137
Layout conditions for Rth(j-a) measurements: board finish thickness 1.6 mm 10 %, board double layer, board dimensions 129 x 60 mm, board Material FR4, Cu thickness 0.070 mm, thermal via separation 1.2 mm, thermal via diameter 0.3 mm 0.08 mm, Cu thickness on vias 0.025 mm. Optional heat sink top layer of 3.5 mm x 25 mm will reduce thermal resistance (see Figure 12).
Fig 11. HTSSOP PCB
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90 Rth(j-a) (K/W) 70
015aaa138
without heatsink top layer 50
with heatsink top layer 30 0 2 4 6 8 PCB Cu heatsink area (cm2) 10
Fig 12. HTSSOP32 thermal resistance junction-to-ambient vs. PCB copper area
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9. Static characteristics
Table 9. Static characteristics Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN = 500 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol VBAT IBAT Parameter battery supply voltage battery supply current MC = 00 (Standby; V1 on) STBCL = 1 (LIN wake-up enabled) WIC1 = WIC2 = 11 (WAKE interrupts enabled); 7.5 V < VBAT < 28 V IV1 = 0 mA; VRSTN = VSCSN = VV1 VTXDL = VV1; VSDI = VSCK = 0 V Tvj = -40 C Tvj = 25 C Tvj = 150 C MC = 01 (Sleep; V1 off) STBCL = 1 (LIN wake-up enabled) WIC1 = WIC2 = 11 (WAKE interrupts enabled); 7.5 V < VBAT < 28 V VV1 = 0 V Tvj = -40 C Tvj = 25 C Tvj = 150 C contributed by LIN wake-up receiver STBCL = 1 VLIN = VBAT; 5.5 V < VBAT < 28 V
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Conditions
Min 4.5
Typ -
Max 28
Unit V
Supply; pin BAT
-
75 68 62
89 80 73
A A A
-
53 49 45 1.1
62 57 51 2
A A A A
contributed by WAKE pin edge detectors; WIC1 = WIC2 = 11 VWAKE1 = VWAKE2 =VBAT 5.1 V < VBAT < 7.5 V 4.5 V < VBAT < 5.1 V V1 on (5 V version) LIN Active mode (recessive) STBCL = 0; MC = 1x VTXDL= VV1; IDLIN = ILIN = 0 mA 5.5 V < VBAT < 28 V LIN Active mode (dominant) STBCL = 0; MC = 1x VTXDL = 0 V; IDLIN = ILIN = 0 mA VBAT = 14 V LIN Active mode (dominant) STBCL = 0; MC = 1x VTXDL= 0 V; IDLIN = ILIN = 0 mA VBAT = 28 V
0
5
10
A
IBAT(add)
additional battery supply current
-
-
50 3 1300
A mA A
-
-
5
mA
-
-
10
mA
Vth(det)pon Vth(det)poff
power-on detection threshold voltage power-off detection threshold voltage
4.5 4.25
-
5.5 4.5
V V
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Table 9. Static characteristics ...continued Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN = 500 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol Vhys(det)pon Vuvd(LIN) Vuvr(LIN) Vhys(uvd)LIN Vuvd(ctrl)Iext Parameter power-on detection hysteresis voltage LIN undervoltage detection voltage LIN undervoltage recovery voltage LIN undervoltage detection hysteresis voltage external current control undervoltage detection voltage output voltage VO(V1)nom = 5 V; VBAT = 5.5 V to 28 V IV1 = -200 mA to -5 mA; CLIN 560 pF VO(V1)nom = 5 V; VBAT = 5.5 V to 28 V IV1 = -200 mA to -5 mA; CLIN 220 pF VO(V1)nom = 5 V; VBAT = 5.5 V to 28 V IV1 = -250 mA to -200 mA VO(V1)nom = 5 V; VBAT = 5.5 V to 5.75 V IV1 = -250 mA to -5 mA 150 C < Tvj < 200 C VO(V1)nom = 5 V; VBAT = 5.75 V to 28 V IV1 = -250 mA to -5 mA 150 C < Tvj < 200 C VO(V1)nom = 3.3 V; VBAT = 4.5 V to 28 V
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Conditions
Min 200 5 5 25 5.9
Typ -
Max 5.3 5.5 300 7.5
Unit mV V V mV V
Voltage source; pin V1 VO 4.9 4.85 4.75 4.5 5 5 5 5 5.1 5.15 5.1 5.1 V V V V
4.85
5
5.1
V
3.234 3.201 2.97
3.3 3.3 3.3
3.366 3.399 3.366
V V V
IV1 = -250 mA to -5 mA; CLIN 560 pF VO(V1)nom = 3.3 V; VBAT = 4.5 V to 28 V IV1 = -250 mA to -5 mA; CLIN 220 pF VO(V1)nom = 3.3 V; VBAT = 4.5 V to 28 V IV1 = -250 mA to -5 mA 150 C < Tvj < 200 C
R(BAT-V1) Vuvd
resistance between pin BAT and pin V1 undervoltage detection voltage
VO(V1)nom = 5 V; VBAT = 4.5 V to 5.5 V IV1 = -250 mA to -5 mA 90 %; VO(V1)nom = 5 V; RTHC = 0 90 %; VO(V1)nom = 3.3 V; RTHC = 0 70 %; VO(V1)nom = 5 V; RTHC = 1 90 %; VO(V1)nom = 5 V; RTHC = 0 90 %; VO(V1)nom = 3.3 V; RTHC = 0 70 %; VO(V1)nom = 5 V; RTHC = 1 IVEXCC = 0 mA
4.5 2.97 3.5 4.56 3.025 3.56 -600
-
3 4.75 3.135 3.75 4.9 3.234 4 -250
V V V V V V mA
Vuvr
undervoltage recovery voltage
IO(sc)
short-circuit output current
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Table 9. Static characteristics ...continued Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN = 500 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol VV1 Parameter voltage variation on pin V1 Conditions as a function of load current variation VBAT = 5.75 V to 28 V IV1 = -250 mA to -5 mA as a function of supply voltage variation VBAT = 5.5 V to 28 V; IV1 = -30 mA VVEXCTRL 4.5 V; VBAT = 6 V to 28 V load current increasing; external PNP transistor connected - see Section 6.6.2 PDC 0 PDC 0; Tvj = 150 C PDC 1 PDC 1; Tvj = 150 C Ith(deact)PNP PNP deactivation threshold current load current falling; external PNP transistor connected - see Section 6.6.2 PDC 0 PDC 0; Tvj = 150 C PDC 1 PDC 1; Tvj = 150 C PNP collector; pin VEXCC Vth(act)Ilim current limiting activation threshold voltage measured across resistor connected between pins VEXCC and V1 (see Section 6.6.2) 2.97 V VV1 5.5 V; 6 V < VBAT < 28 V VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V 240 330 mV 40 44 11 12 76 50 22 15 120 59 36 18 mA mA mA mA 74 74 44 44 130 85 76 50 191 99 114 59 mA mA mA mA Min Typ Max 25 Unit mV Load regulation
Line regulation VV1 voltage variation on pin V1 25 mV
PNP base; pin VEXCTRL IO(sc) Ith(act)PNP short-circuit output current PNP activation threshold current 3.5 5.8 8 mA
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Serial peripheral interface inputs; pins SDI. SCK and SCSN Vth(sw) Vhys(i) Rpd(SCK) Rpu(SCSN) ILI(SDI) switching threshold voltage input hysteresis voltage pull-down resistance on pin SCK pull-up resistance on pin SCSN input leakage current on pin SDI HIGH-level output current LOW-level output current output leakage current VSCSN = 0 V; VO = VV1 - 0.4 V VV1 = 2.97 V to 5.5 V VSCSN = 0 V; VO = 0.4 V VV1 = 2.97 V to 5.5 V VSCSN = VV1; VO = 0 V to VV1 VV1 = 2.97 V to 5.5 V 0.3VV1 100 50 50 -5 130 130 0.7VV1 900 400 400 +5 V mV k k A
Serial peripheral interface data output; pin SDO IOH IOL ILO -30 1.6 -5 -1.6 30 5 mA mA A
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Table 9. Static characteristics ...continued Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN = 500 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol IOH IOL Parameter HIGH-level output current LOW-level output current Conditions VRSTN = 0.8VV1 VV1 = 2.97 V to 5.5 V strong; VRSTN = 0.2VV1 VV1 = 2.97 V to 5.5 V -40 C < Tvj < 200 C weak; VRSTN = 0.8VV1 VV1 = 2.97 V to 5.5 V -40 C < Tvj < 200 C VOL LOW-level output voltage VV1 = 1 V to 5.5 V pull-up resistor to VV1 900 -40 C < Tvj < 200 C; VBAT < 28 V IR(V1-BAT) < 25 mA VV1 = 2.975 V to 5.5 V pull-up resistor to V1 900 -40 C < Tvj < 200 C VOH Vth(sw) Vhys(i) IOL IOH HIGH-level output voltage switching threshold voltage input hysteresis voltage LOW-level output current HIGH-level output current -40 C < Tvj < 200 C VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V VOL = 0.4 V VOH = VV1 - 0. 4 V VV1 = 2.97 V to 5.5 V VOL = 0.4 V; VV1 = 2.97 V to 5.5 V IOL = 20 A; VV1 = 1.5 V VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V Min -1500 4.9 Typ Max -100 40 Unit A mA Reset output with clamping detection; pin RSTN
200
-
540
A
0
-
0.2VV1
V
0
-
0.5
V
0.8VV1 0.3VV1 100 1.6 -20 1.6 -
VV1 + 0.3 0.7VV1 900 15 -1.6 20 0.4 0.7VV1 900 20 3.75 1000 0 2 8
V V mV mA mA mA V V mV k V mV A A mA
Interrupt output; pin INTN Enable output; pin EN
LOW-level output current IOL www..com VOL Vth(sw) Vhys(i) Rpupd Vth(sw) Vhys(i) Ipu Ipd IO LOW-level output voltage switching threshold voltage input hysteresis voltage pull-up/pull-down resistance switching threshold voltage input hysteresis voltage pull-up current pull-down current output current Watchdog off input; pin WDOFF
0.3VV1 100 5 2 100 10 -
Wake input; pin WAKE1, WAKE2
VWAKE = 0 V for t < twake VWAKE = VBAT for t < twake VLIMP = 0.4 V; LHWC = LHC = 1 Tvj = -40 C to 200 C VWBIAS = 1.4 V VV1 = 2.97 V to 5.5 V
-2 0 0.8
Limp home output; pin LIMP
Wake bias output; pin WBIAS IO Vth(sw)
UJA1079_1
output current switching threshold voltage
1
-
7 0.7VV1
mA V
LIN transmit data input; pin TXDL 0.3VV1 -
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Table 9. Static characteristics ...continued Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN = 500 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol Vhys(i) Rpu IOH IOL Rpu IBUS_LIM IBUS_PAS_rec IBUS_PAS_dom Parameter input hysteresis voltage pull-up resistance HIGH-level output current LOW-level output current pull-up resistance current limitation for driver dominant state receiver recessive input leakage current receiver dominant input leakage current including pull-up resistor loss of ground leakage current loss of battery leakage current receiver recessive voltage receiver dominant voltage receiver center threshold voltage receiver hysteresis threshold voltage external capacitance dominant output voltage LIN Active mode; VRXDL = VV1 - 0.4 V VRXDL= 0.4 V MC = 00; Standby mode LIN Active mode; VBAT = VLIN = 18 V VTXDL = 0 V VLIN = 28 V; VBAT = 5.5 V; VTXDL = VV1 VTXDL = VV1; VLIN = 0 V; VBAT = 14 V Conditions VV1 = 2.97 V to 5.5 V Min 100 4 -20 1.6 4 40 -10 Typ 12 12 Max 900 25 -1.5 20 25 100 2 +10 Unit mV k mA mA k mA A A
LIN receive data output; pin RXDL
LIN bus line; pin LIN
IL(log) IL(lob) Vrec(RX) Vdom(RX) Vth(cntr)RX
VBAT = VGND = 28 V; VLIN = 0 V VBAT = 0 V; VLIN = 28 V VBAT = 5.5 V to 18 V VBAT = 5.5 V to 18 V Vth(cntr)RX = (Vth(rec)RX + Vth(dom)RX)/2 VBAT = 5.5 V to 18 V LIN Active/Lowpower modes Vth(hys)RX = Vth(rec)RX - Vth(dom)RX VBAT = 5.5 V to 18 V LIN Active/Lowpower modes on pin LIN LIN Active mode; VTXDL = 0 V VBAT = 7 V LIN Active mode; VTXDL = 0 V VBAT = 18 V
-100 0.6 x VBAT -
-
10 2 -
A A V
0.4VBAT V 0.525 x VBAT 0.175 x VBAT 30 1.4 2.0 V
0.475 0.5 x x VBAT VBAT 0.05 x VBAT 0.15 x VBAT -
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Vth(hys)RX
V
Cext VO(dom)
pF V V
LIN bus termination; pin DLIN V(DLIN-BAT) voltage difference between pin DLIN and pin BAT overtemperature protection activation threshold temperature overtemperature protection release threshold temperature 5 mA < IDLIN < 20 mA 0.4 0.65 1 V
Temperature protection Tth(act)otp 165 180 200 C
Tth(rel)otp
126
138
150
C
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LIN core system basis chip
10. Dynamic characteristics
Table 10. Dynamic characteristics Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN = 500 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol td(uvd) tdet(CL)L Parameter undervoltage detection delay time Conditions VV1 falling; dVV1/dt = 0.1 V/s Min 7 95 Typ Max 23 140 Unit s ms Voltage source; pin V1
LOW-level clamping detection VV1 < 0.9VO(V1)nom; V1 active time clock cycle time SPI enable lead time SPI enable lag time clock HIGH time clock LOW time data input set-up time data input hold time data output valid time chip select pulse width HIGH reset pulse width HIGH-level clamping detection time filter time filter time wake-up time power-on delay time duty cycle 1 Vth(rec)RX(max) = 0.744VBAT Vth(dom)RX(max) = 0.581VBAT; tbit = 50 s VBAT = 7 V to 18 V; LSC = 0 Vth(rec)RX(max) = 0.76VBAT Vth(dom)RX(max) = 0.593VBAT; tbit = 50 s VBAT = 5.5 V to 7 V; LSC = 0
[1] [2]
Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO tcy(clk) tSPILEAD tSPILAG tclk(H) tclk(L) tsu(D) th(D) tv(Q) tWH(S) tw(rst) t VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V; clock is LOW when SPI select falls VV1 = 2.97 V to 5.5 V; clock is LOW when SPI select rises VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V pin SDO; VV1 = 2.97 V to 5.5 V CL = 100 pF VV1 = 2.97 V to 5.5 V long; Ipu(RSTN) < 100 A; no pull-up short; Rpu(RSTN) = 900 to 1100
det(CL)H www..com
320 110 140 160 160 0 80 20 20 3.6 95 7 0.9 10 113 0.396
-
110 25 5 140 18 2.3 40 278 -
ns ns ns ns ns ns ns ns ns ms ms ms s ms s s
Reset output; pin RSTN
RSTN driven HIGH internally but RSTN remains LOW
tfltr tfltr twake td(po) 1
Watchdog off input; pin WDOFF Wake input; pin WAKE1, WAKE2
LIN transceiver; pins LIN, TXDL, RXDL
[1] [2]
0.396
-
-
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UJA1079
LIN core system basis chip
Table 10. Dynamic characteristics ...continued Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN = 500 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol 2 Parameter duty cycle 2 Conditions Vth(rec)RX(min) = 0.422VBAT Vth(dom)RX(min) = 0.284VBAT; tbit = 50 s VBAT = 7.6 V to 18 V; LSC = 0 Vth(rec)RX(min) = 0.41VBAT Vth(dom)RX(min) = 0.275VBAT; tbit = 50 s VBAT = 6.1 V to 7.6 V; LSC = 0 3 duty cycle 3 Vth(rec)RX(max) = 0.778VBAT Vth(dom)RX(max) = 0.616VBAT tbit = 96 s; VBAT = 7 V to 18 V LSC = 1 Vth(rec)RX(max) = 0.797VBAT Vth(dom)RX(max) = 0.630VBAT tbit = 96 s; VBAT = 5.5 V to 7 V LSC = 1 4 duty cycle 4 Vth(rec)RX(min) = 0.389VBAT Vth(dom)RX(min) = 0.251VBAT; tbit = 96 s VBAT = 7.6 V to 18 V; LSC = 1 Vth(rec)RX(min) = 0.378VBAT Vth(dom)RX(min) = 0.242VBAT; tbit = 96 s VBAT = 6.1 V to 7.6 V; LSC = 1 tPD(RX)r tPD(RX)f tPD(RX)sym tbus(dom)(min)
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[2] [3]
Min -
Typ -
Max 0.581
Unit
[2] [3]
-
-
0.581
[1] [2]
0.417
-
-
[1] [2]
0.417
-
-
[2] [3]
-
-
0.590
[2] [3]
-
-
0.590
rising receiver propagation delay falling receiver propagation delay receiver propagation delay symmetry minimum dominant bus time
VBAT = 5.5 V to 18 V; RRXDL = 2.4 k CRXDL = 20 pF VBAT = 5.5 V to 18 V; RRXDL = 2.4 k CRXDL = 20 pF VBAT = 5.5 V to 18 V; RRXDL = 2.4 k CRXDL = 20 pF for wake-up of the LIN transceiver
[4]
-2 28 20 227
-
6 6 +2 104 80 278 71.2 17.8 0.555 x NWP[6] 1.11 x NWP[6] 563.2
s s s s ms s ms ms ms ms
tto(dom)TXDL
TXDL dominant time-out time LIN online mode; VTXDL = 0 V WBIAS LOW time cycle time WBC = 1 WBC = 0
Wake bias output; pin WBIAS tWBIASL tcy Watchdog ttrig(wd)1 ttrig(wd)2 Oscillator fosc
[1] [2] [3]
58.1 14.5
[5]
watchdog trigger time 1 watchdog trigger time 2
Normal mode watchdog Window mode only Normal, Standby and Sleep modes watchdog Window mode only
0.45 x NWP[6] 0.9 x NWP[6] 460.8 512
[7]
oscillator frequency t bus ( rec ) ( min ) 1, 3 = ------------------------------- . 2 x t bit
kHz
Bus load conditions are: CL = 1 nF and RL = 1 k; CL = 6.8 nF and RL = 660 ; CL = 10 nF and RL = 500 .
t bus ( rec ) ( max 2, 4 = -------------------------------) . 2 x t bit
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Product data sheet
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[4] [5] [6] [7]
tPD(RX)sym = tPD(RX)r - tPD(RX)f. A system reset will be performed if the watchdog is in Window mode and is triggered less than ttrig(wd)1 after the start of the watchdog period (or in the first half of the watchdog period). The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Table 4); valid in watchdog Window mode only. The watchdog will be reset if it is in window mode and is triggered at least ttrig(wd)1, but not more than ttrig(wd)2, after the start of the watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than ttrig(wd)2 after the start of the watchdog period (watchdog overflows).
BAT RXDL CRXDL TXDL GND DLIN RLIN LIN CLIN
SBC
015aaa128
Fig 13. Timing test circuit for LIN transceiver
tbit VTXDL
tbit
tbit
tbus(rec)(min) VBAT Vth(rec)RX(max)
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Vth(dom)RX(max) Vth(rec)RX(min) Vth(dom)RX(min)
thresholds of receiving node A
thresholds of receiving node B
tbus(rec)(max) output of receiving node A VRXDL
output of receiving node B
tPD(RX)f VRXDL
tPD(RX)r
tPD(RX)r
tPD(RX)f
015aaa133
Fig 14. Timing diagram LIN transceiver
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LIN core system basis chip
SCS tSPILEAD Tcy(clk) tclk(H) tclk(L) tSPILAG tWH(S)
SCK
tsu(D)
th(D)
SDI
X
MSB tv(Q)
LSB
X
floating SDO X MSB LSB
floating
015aaa045
Fig 15. SPI timing
11. Test information
11.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications.
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12. Package outline
HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
SOT549-1
D
E
A X
c y exposed die pad side HE vMA
Z
Dh
32
17
Eh pin 1 index
A2 A1
(A3)
A
Lp L
1
16
e bp wM
detail X
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0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.09 D(1) 11.1 10.9 Dh 5.1 4.9 E(2) 6.2 6.0 Eh 3.6 3.4 e 0.65 HE 8.3 7.9 L 1 Lp 0.75 0.50 v 0.2 w 0.1 y 0.1 Z 0.78 0.48
8o o 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT549-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-04-07 05-11-02
Fig 16. Package outline SOT549-1 (HTSSOP32)
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LIN core system basis chip
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
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* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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LIN core system basis chip
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 17) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12
Table 11. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 12. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6
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Package thickness (mm)
350 220 220
Package thickness (mm)
350 to 2000 260 250 245
> 2000 260 245 245
260 260 250
1.6 to 2.5 > 2.5
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 17.
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LIN core system basis chip
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 17. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
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14. Revision history
Table 13. Revision history Release date 20091201 Data sheet status Product data sheet Change notice Supersedes Document ID UJA1079_1
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15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such www..com information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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LIN core system basis chip
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Power management . . . . . . . . . . . . . . . . . . . . . 2 2.4 Control and Diagnostic features . . . . . . . . . . . . 2 2.5 Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . 3 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 System Controller . . . . . . . . . . . . . . . . . . . . . . . 6 6.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.1.2 Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1.3 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1.4 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1.5 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.1.6 Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . 10 6.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2.3 WD_and_Status register. . . . . . . . . . . . . . . . . 12 6.2.4 Mode_Control register . . . . . . . . . . . . . . . . . . 13 6.2.5 Int_Control register . . . . . . . . . . . . . . . . . . . . . 14 6.2.6 Int_Status register. . . . . . . . . . . . . . . . . . . . . . 15 6.3 On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 16 6.4 Watchdog (UJA1079/xx/WD versions) . . . . . . 16 6.4.1 Watchdog Window behavior . . . . . . . . . . . . . . 16 6.4.2 Watchdog Timeout behavior . . . . . . . . . . . . . . 17 www..com 6.4.3 Watchdog Off behavior . . . . . . . . . . . . . . . . . . 17 6.5 System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.5.1 RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5.2 EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5.3 LIMP output . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.6 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 19 6.6.1 Battery pin (BAT) . . . . . . . . . . . . . . . . . . . . . . 19 6.6.2 Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . 19 6.7 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 21 6.7.1 LIN operating modes . . . . . . . . . . . . . . . . . . . 21 6.7.1.1 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.7.1.2 Lowpower/Off modes . . . . . . . . . . . . . . . . . . . 22 6.7.2 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . 22 6.7.2.1 General fail-safe features . . . . . . . . . . . . . . . . 22 6.7.2.2 TXDL dominant time-out function . . . . . . . . . . 22 6.8 Local wake-up input . . . . . . . . . . . . . . . . . . . . 22 6.9 6.10 7 8 9 10 11 11.1 12 13 13.1 13.2 13.3 13.4 14 15 15.1 15.2 15.3 15.4 16 17 Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . Temperature protection . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Test information . . . . . . . . . . . . . . . . . . . . . . . Quality information . . . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 25 27 29 34 37 37 38 39 39 39 39 40 42 43 43 43 43 43 43 44
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 December 2009 Document identifier: UJA1079_1

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